adam-maj / tiny-gpu
A minimal GPU design in Verilog to learn how GPUs work from the ground up
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A minimal GPU design in Verilog to learn how GPUs work from the ground up
OpenTitan: Open source silicon root of trust
RISC-V Debug Support for our PULP RISC-V Cores
OpenSource GPU, in Verilog, loosely based on RISC-V ISA
Generic Register Interface (contains various adapters)
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
A minimal Linux-capable 64-bit RISC-V SoC built around CVA6
Common SystemVerilog components