vhdl

Home Brew 8 Bit CPU Hardware Implementation including a Verilog simulation, an assembler, a "C" Compiler and this repo also contains my research and learning. See also the Hackaday.IO project. https://hackaday.io/project/166922-spam-1-8-bit-cpu

design cpu vhdl assembler verilog rom ttl alu 8bit cmos verilog-components logism homebrew-cpu

Updated Aug 27, 2023
Verilog

pontazaricardo / Verilog_Calculator_Matrix_Multiplication

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This is a simple project that shows how to multiply two 3x3 matrixes in Verilog.

calculator vhdl matrix-multiplication verilog xilinx hardware-designs xilinx-fpga low-level-programming xilinx-ise xilinx-vivado ic-design

Updated Aug 12, 2017
Verilog

Archfx / FPGA-stereo-Camera-Basys3

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Integration of two camera 📷 modules to Basys 3 FPGA

fpga vhdl verilog

Updated Feb 8, 2023
Verilog

abdelazeem201 / Design-and-ASIC-Implementation-of-32-Point-FFT-Processor

Star

I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. A single-path delay commutator processing element (SDC PE) has been proposed for the first time. It saves a complex adder compared with the typical radix-2 butterfly unit. The new pipelined architecture can be …

asic fpga vhdl rtl verilog synthesis fft soc asic-verification asic-design

Updated Dec 3, 2023
Verilog

micro-FPGA / CRUVI

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CRUVI Standard Specifications

fpga vhdl verilog litex

Updated May 6, 2024
Verilog

OrsuVenkataKrishnaiah1235 / RTL-Coding

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"Mastering Verilog Programming for Digital Circuit Design: RTL and TestBench Codes Practice with HDL-BITS"

fpga vhdl rtl verilog hdlbits asic-design rtl-design-and-verification rtl-coding hdlbitssolution

Updated Aug 13, 2023
Verilog

amamory-verification / hw-formal-verif

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Hardware Formal Verification

vhdl model-checking systemverilog formal-verification fault-simulation equivalence-checker jasper-gold

Updated Aug 10, 2020
Verilog

Multimedia-Processing / Digital-Logic-Design

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透過數位邏輯結合VHDL與Verilog的過程，作為從基礎數位邏輯到計算機系統結構，並實作出一顆CPU的教學書籍，希望未來可以成為教學範例檔案。目前將開發轉移到GitLab，因為可以呈現數學與MUL圖。

Updated Oct 25, 2023
Verilog

Nidhinchandran47 / my_rtl_code

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Repository for RTL building blocks #100daysofrtl VERILOG VHDL System Verilog

fpga vhdl verilog hdl vlsi system-verilog verilog-hdl verilog-programs verilog-project rtl-coding

Updated Jun 3, 2024
Verilog

nicolavianello95 / RISC-V

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Design, verification and ASIC implementation of a complete RISC-V CPU with: five stages pipeline, forwarding, automatic hazard detection, Branch Target Buffer using LRU replacement policy, absolute value custom instruction.

asic cpu vhdl forwarding hazard-detection risc-v branch-target-buffer

Updated Apr 12, 2020
Verilog

egk696 / EDAC_SDRAM_Controller

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Mitigating Single-Event Upsets in COTS SDRAM using an EDAC SDRAM Controller

fpga vhdl embedded-systems vivado fault-tolerant quartus-prime sdram sdram-controller cots-sdram

Updated Oct 30, 2017
Verilog

abdelazeem201 / ASIC-Implementation-UART

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This paper presents design of UART module for serial communication used for short-distance, low speed and exchange of data between computer and peripherals. UART mainly contains Transmitter, Receiver and Baud Rate Generator. Baud Rate Generator generates the clock for the UART. We can achieve the desired Baud Rate by using divide factor from sys…

asic fpga vhdl eda rtl verilog synthesis uart soc pnr

Updated Mar 30, 2022
Verilog

fjpolo / CourseraFPGADesignforEmbeddedSystemsSpecialization

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Projects and labs from the courses dictated in https://www.coursera.org/specializations/fpga-design. Projects are sometimes simulated, and implemented in either a MAX10-Lite or an Arrow MAX1000 board.-

fpga arrow vhdl intel coursera rtl verilog altera hdl vlsi max10 max1000 max10-lite

Updated Mar 22, 2021
Verilog

arhamhashmi01 / rv32i-pipeline-processor

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This repository contain the implementaton of RV32I 5-Stage-Pipeline-Processor based on RISC-V ISA and designed on Verilog

vhdl verilog microprocessor hardware-designs computer-architecture gtkwave vlsi pipeline-processor risc-v rv32i verilator asic-design chip-design 5-stage-pipelined-processor rv32i-processor

Updated Mar 22, 2024
Verilog

abdelazeem201 / ORCA

Star

Multi-Voltage and Multi-Threshold Low Power Design Techniques for ORCA Processor Based on 32 nm Technology

asic vhdl rtl verilog synthesis synopsys hdl fpga-soc pnr upf asic-design synopsys-vcs synopsys-dc systemonchip synopsys-iccii saed32nm

Updated Sep 10, 2023
Verilog

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vhdl

Here are 94 public repositories matching this topic...

antonblanchard / microwatt

open-sdr / openwifi-hw

sergeykhbr / riscv_vhdl

im-tomu / fomu-workshop

thedatabusdotio / fpga-ml-accelerator

Johnlon / spam-1

pontazaricardo / Verilog_Calculator_Matrix_Multiplication

Archfx / FPGA-stereo-Camera-Basys3

abdelazeem201 / Design-and-ASIC-Implementation-of-32-Point-FFT-Processor

micro-FPGA / CRUVI

OrsuVenkataKrishnaiah1235 / RTL-Coding

amamory-verification / hw-formal-verif

Multimedia-Processing / Digital-Logic-Design

Nidhinchandran47 / my_rtl_code

nicolavianello95 / RISC-V

egk696 / EDAC_SDRAM_Controller

abdelazeem201 / ASIC-Implementation-UART

fjpolo / CourseraFPGADesignforEmbeddedSystemsSpecialization

arhamhashmi01 / rv32i-pipeline-processor

abdelazeem201 / ORCA

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