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Achievements

Achievement: Pull Sharkx3Achievement: QuickdrawAchievement: Pair ExtraordinaireAchievement: YOLO
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NadeemYaseen/README.md
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Hi there 👋

Welcome to my digital playground, where logic dances with circuits and automation fuels innovation! I'm a passionate engineer fueled by automation and hardware design verification, specializing in:

  • 🛠️ EDA Tools Automation: Scripting magic with Python, BASH, and TCL to tame the beasts of EDA tools like Synopsys.
  • Python Python Mastery: From data crunching to automation scripts, I wield Python like a Jedi lightsaber, slicing through complexity with elegance.
  • 🛣️ BASH & TCL Fu: Shell scripting is my playground, crafting custom commands and automating workflows with BASH and TCL like a seasoned architect. ️
  • 🛢️ CMake & Make Magic: Building complex projects is a breeze with my CMake and Make expertise, weaving dependencies into a tapestry of efficiency. ‍♂️
  • LinuxLinux Commando: The terminal is my canvas, and Linux commands are my brushes. I navigate systems with the agility of a seasoned explorer.
  • GitHub GitHub Actions Guru: Orchestrating workflows and automating tasks? You got it! I'm your GitHub Actions sensei, crafting CI/CD pipelines that sing.
  • 🌐 SystemVerilog & UVM Whisperer: Hardware verification is my domain, whereas SystemVerilog and UVM are my loyal companions, sniffing out bugs and ensuring robust designs.
  • 🕵️ Hardware Debugging Ninja: Glitches and errors tremble before me! I wield various EDA tools like a seasoned samurai, dissecting hardware issues with precision and finesse.

🛠️ Languages and Tools :

BASH  CMake  Markdown  C++  Python  Linux  Docker  Git  GitHub  Vim  GCC 

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🔥 My Stats :

GitHub Streak

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Popular repositories

  1. vsd_IAT_openlane_workshop vsd_IAT_openlane_workshop Public

    It contains the material that was studied and learned in a 5 day workshop from 25 to 29 November conducted by Kunal Ghosh, co-founder of VLSI System Design (VSD) Corp. Pvt. Ltd.

    1

  2. vsdPLLSoC vsdPLLSoC Public

    Forked from rsnkhatri3/vsdPLLSoC

    Verilog

  3. Nadeem-Yaseen Nadeem-Yaseen Public

    Config files for my GitHub profile.

  4. LM-RISCV-DV LM-RISCV-DV Public

    Forked from Lampro-Mellon/LM-RISCV-DV

    An Open-Source Design and Verification Environment for RISC-V

    SystemVerilog

  5. Raptor Raptor Public

    Forked from os-fpga/Raptor

    Raptor end-to-end FPGA Compiler and GUI

    Verilog

  6. contentMK contentMK Public