MIPS32

Pipelined MIPS32 Processor Built in Verilog

This is a pipelined 32 bit MIPS processor built in verilog that was completed in my Organization of Digital Computers Laboratory class. This design fufills the majority of the MIPS32 design spec, with the ALU_OP codes being slightly different from the actual ISA in order to comply with how the professor had designed the grading testbench.

In order to see the processor in action, Import all files into Vivado and run the behavioral simulation.

Some screenshots:

Name		Name	Last commit message	Last commit date
Latest commit History 2 Commits
images		images
ALU.v		ALU.v
ALUControl.v		ALUControl.v
EX_Forwarding_unit.v		EX_Forwarding_unit.v
EX_pipe_stage.v		EX_pipe_stage.v
Hazard_detection.v		Hazard_detection.v
ID_pipe_stage.v		ID_pipe_stage.v
IF_pipe_stage.v		IF_pipe_stage.v
README.md		README.md
control.v		control.v
data_memory.v		data_memory.v
instruction_mem.v		instruction_mem.v
mips_32.v		mips_32.v
mux.v		mux.v
mux4.v		mux4.v
pipe_reg.v		pipe_reg.v
pipe_reg_en.v		pipe_reg_en.v
register_file.v		register_file.v
sign_extend.v		sign_extend.v
tb_mips_32.v		tb_mips_32.v

0xjmux/MIPS32

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MIPS32

Waveform showing data forwarding

Waveform showing Data Hazard Avoidance

Successful Testbench Output

FPGA Utilization Graph

Power Utilization

Processor Schematic

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